This invention relates to a non-volatile semiconductor memory device having a floating gate and a control gate, and a method for manufucturing the same.
An ultra-violet erase type non-volatile memory (EPROM) has a memory cell, which is a MOS transistor with a floating gate and a control gate.
A memory cell of an EPROM in the prior art will be explained below with reference to FIG. 1.
N-type source and drain regions 118 and 119 are formed in the surface portions of a p-type silicon semiconductor substrate 111. A first SiO.sub.2 layer 112 is formed on a channel region 122 between the source region 118 and the drain region 119. A floating gate 113 of poly-silicon is formed on the first SiO.sub.2 layer 112.
A second SiO.sub.2 layer 114, a silicon nitride layer 115 and a third SiO.sub.2 layer 116 are formed in that order on the floating gate 113, and a control gate 117 of poly-silicon is formed on the third SiO.sub.2 layer 116.
A fourth SiO.sub.2 layer 120 is formed by thermal oxidation on a surface of the floating gate 113 and the control gate 117. During this thermal oxidation, thick oxide portions 120A and 120B are simultaneously formed at each end of the floating gate 113.
The operation of this memory cell is explained as follows.
By applying 12.5,7 and 0 V to the control gate 117, the drain region 119 and the source region 118, hot electrons are generated and injected into the floating gate 113. Thus, data "0" is written into this memory cell.
By exposing this memory cell to ultra-violet rays, electrons are discharged from the floating gate 113. Therefore, data "1" is written into this memory cell.
The Tech Digest of IEDM, p. 714 and p. 721, 1987 teaches that a large leakage current flows from the edge of a drain region to a silicon substrate in a MOSFET type semiconductor device because of the thin gate oxide film in the device.
When electrons are present in a floating gate of an EPROM cell, such leakage current increases conspicuously because the potential of the floating gate is negative.
In the memory cell of FIG. 1, electrons in the floating gate can disappear and data may be destroyed. In this case, it is believed that holes are generated by this leakage current and are injected into the floating gate. In the memory cell of FIG. 1, such leakage current is suppressed by the thick oxide portions 120A and 120B.
In order to erase the data by exposing the memory cell to ultra-violet rays, electrons stored in the floating gate 113 are discharged to the source region 118 and the drain region 119 through the thick oxide portions 120A and 120B, and to the control gate 117.
The silicon nitride 115 formed for obtaining a dielectric constant extends in the length direction of the channel region 122 beyond the edge of the floating gate 113 and the control gate 117, and it is harder for electrons to pass through silicon nitride as compared with SiO.sub.2.
Therefore, most of the electrons are discharged to the source region 118 and the drain region 119. However, such discharge to the source and drain regions arises at the edge portions of the floating gate, so that electrons pass through the thick oxide portions 12OA and 120B during the erasing of data.
Moreover, the existence of thick oxide in source side 12a may lead to the increase of palasitic resistance and degradation of drivability for cell transistor.
Accordingly, in the prior art, there was a problem in that the speed of erasing data was reduced and current drivability of cell transistor may degrade because of the existence of the thick oxide portions 120A and 120B.